The present invention relates, in general, to public-key cryptography and, more particularly, to a public-key cryptographic integrated circuit.
Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) are public-key cryptographic algorithms that provide high security for digital data transfers between electronic devices. The modular mathematics of the RSA and ECC (Fp) algorithms can be computed on a hardware multiplier and the polynomial mathematics of the ECC (F2M in polynomial-basis) algorithm can be computed on a different hardware multiplier. Both hardware multiplier architectures that are used for computing the RSA and ECC algorithms can use pipelining techniques for the massive parallel computations of the algorithms. The pipelined multiplier offers lower power which is required for many applications.
Hardware implementations for computing RSA and ECC algorithms is not straight forward. Thus, the type of cryptography best suited for the system application defines the appropriate hardware multiplier architecture that computes the desired RSA or ECC algorithms. With increasing demand for faster cryptographic operations and higher performance, hardware modular multiplier architecture improvements are needed to ensure high levels of security.
Accordingly, it would be advantageous to provide cryptography in a multiplication system that achieves high performance, low cost, and low-power for implementation in an integrated circuit. It would be a further advantage for the multiplication system to compute the RSA and ECC algorithms.